Extremely low on-resistances have been achieved in vertical power MOSFET technology by scaling down the breakdown voltage of the power device and by introducing trench gate structures. The advent of these ultra-low on-resistance power MOSFETs has re-emphasized the importance of minimizing parasitic resistance in the semiconductor package and in the metal interconnects on the surface of the die. This question is discussed in an article entitled "Benefits of DMOS Voltage Scaling on Synchronous Buck Regulator Efficiency", International Symposium on Power Semiconductor Devices (1993), p. 141, FIG. 5, incorporated herein by reference in its entirety.
A vertical power transistor, exemplified in FIG. 1A, is a device in which the current flows vertically from a surface of the die to a region in the interior of or on the opposite surface of the die. For example, in the trench MOSFET illustrated in FIG. 1A, electrons flow from a source region 10 through a body region 11 and a lightly-doped or "drift region" 12, to a drain region 13. The flow of current is controlled by a gate 14, which is formed in a trench 15. When gate 14 is turned on, a channel region forms within body region 11 at the surface of the trench 15. A drain contact may be formed on the bottom surface of the structure, or in so-called "quasi-vertical" devices, the drain may be contacted from the top surface of the die through, for example, a "sinker" extending downward from the top surface to the substrate.
Contact with the source regions, which are typically shorted to the body region, is made by a thin metal layer 16 which is frequently deposited by evaporation or sputtering. FIG. 1B shows a top view of thin metal layer 16 on a die 17. As is apparent, thin metal layer 16 covers essentially the entire top surface of the die, with the exception of locations reserved for the gate pad, buses used to contact the gate, and a narrow strip around the perimeter of the die. FIG. 1C shows a detailed view of an area 16A of the thin metal layer 16, which reveals that gate 14 is actually formed in a grid pattern which surrounds individual cells 18, which include the exposed surfaces of source region 10 and body region 11. Within each cell 18, the exposed surface of source 10 surrounds the exposed surface of body 11.
If it is assumed that the metal layer is sufficiently conductive that no voltage drop occurs across the surface of the die, then the source contact of every cell can be assumed to be shorted to the other source contacts, i.e., that the cells are connected in parallel as shown in the schematic drawing of FIG. 2, wherein the bond wire resistance is represented as R.sub.wire. In such a case, the bond wire resistance does indeed look like an ideal series element even if more than one bond wire is used. For MOSFETs having a resistance over several hundred milliohms, this assumption is generally valid.
This assumption is not valid at lower resistances, however, particularly where the resistance of the MOSFETs are reduced by voltage scaling or by high density trench gate technologies. For MOSFET 30 shown in FIG. 3A, for example, if the metal layer 31 contributes a non-negligible resistance, the equivalent circuit of the MOSFET must include resistors interposed between each source contact, as shown in FIG. 3B. In FIG. 3B, R.sub.wire represents the resistance of the bond wire, and R.sub.metal represents the resistance of the metal layer 31 between each source contact. The transistors (e.g., MOSFET 32) that are located furthest from the bond wire location will have a higher series resistance than those (e.g., MOSFET 33) that are located close to the bond wire. Accordingly, the MOSFET cells cannot be considered in parallel, and the device will have a higher overall on-resistance than otherwise expected.
Increasing the thickness of metal layer 31 prior to the formation of the passivation layer is not a solution to the problem. First of all, the thickness that can be practically fabricated is limited to about 4 .mu.m, and this is an order of magnitude thinner than what would be required to ignore the metal resistance in a 60 V trench or 30 V planar double-diffused (DMOS) device. Moreover, fabricating a thick metal layer risks cracking the passivation layer where the passivation layer overlaps the metal at the die edge (referred to as the "junction termination") or along gate buses within the device. The deposition and etching of a thick metal layer is also a problem and may be incompatible with the fabrication equipment. For example, long metal deposition cycles suffer from the effects of target heating and target depletion which require the use of multiple source targets. Dry etching a thick metal layer requires a very thick layer of photoresist (e.g., 6 .mu.m), as compared to a standard thickness of about 1 .mu.m. Wet etching of a thick metal layer requires large metal-to-metal spacings (e.g., 15 .mu.m) and may produce notches ("mouse bites") on the gate bus lines.
As shown in the top view of FIG. 4, multiple source bond wires have been used in an effort to "short out" the resistance of the metal layer 31. However, as shown in the equivalent circuit of FIG. 5, this is only a partial solution. Since each bond wire may have a resistance of 30-50 m.OMEGA., the extra bond wires do not fully compensate for the resistance of the metal layer. Moreover, the pinout of the MOSFET package may not accommodate the number of bonding wires desired or the ideal placement of the wires. The resulting non-uniformity in current distribution is shown in FIG. 5 of an article by Frank Goodenough entitled "P-DMOSFET and TSSOP Turns On With 2.7 V.sub.gs ". Electronic Design, May 2, 1994, pp. 89-95, incorporated herein by reference in its entirety, which qualitatively describes the higher equivalent resistance of the die.
The resistance attributable to the metal layer may account for a significant percentage of the total resistance of a power MOSFET. For example, in a 12 m.OMEGA. MOSFET, the metal layer resistance may account for a full 5 m.OMEGA. of the total.
The problem is so severe that in some cases extreme solutions have been attempted. One such approach is "stitch bonding", shown in FIGS. 6A and 6B, wherein the bonding wire is repeatedly bonded to the surface of the die in a snake-like pattern. This approach suffers from numerous problems. It takes specialized bonding equipment. The bond wire must follow a straight line while avoiding the gate buses. This may not be possible in a particular die. Moreover, the number and angles of the stitch bonds may not be compatible with a given package and pinout, and the repeated bonding at close spacing subjects the die to a higher mechanical stress than normal wire bonding. The multiple bonds also take longer than normal bonding, so that production throughput is reduced.
Accordingly, what is needed is a simple, cost-effective technique for reducing the distributed resistance of the source metal layer in a vertical power transistor. The ideal solution would not influence the spacing between the source metal and the gate metal, would readily permit wire-bonding with gold or aluminum wire, and would not adversely affect the integrity of the passivation layer at the edge of the die or along any metal step. Finally, the solution should not require more than one source bond wire (except to reduce the wire resistance itself) and should not place any restrictions on the placement or angle of the source bond wire.